2778 search results - page 342 / 556 » Reuse Technique in Hardware Design |
186
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ISLPED
2004
ACM
16 years 4 days ago
2004
ACM
Microprocessor designers use techniques such as clock gating to reduce power dissipation. An unfortunate side-effect of these techniques is the processor current fluctuations th...
165
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ICCD
2007
IEEE
16 years 3 months ago
2007
IEEE
This paper explores statistical simulation as a fast simulation technique for driving chip multiprocessor (CMP) design space exploration. The idea of statistical simulation is to ...
218
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ICCD
2005
IEEE
16 years 3 months ago
2005
IEEE
Increasingly significant power/ground supply voltage degradation in nanometer VLSI designs leads to system performance degradation and even malfunction. Existing techniques focus...
164
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ICCAD
2008
IEEE
16 years 3 months ago
2008
IEEE
— Three-dimensional die stacking integration provides the ability to stack multiple layers of processed silicon with a large number of vertical interconnects. Through Silicon Via...
193
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DATE
2009
IEEE
16 years 1 months ago
2009
IEEE
Carbon Nanotube Field-Effect Transistors (CNFETs) show big promise as extensions to silicon-CMOS because: 1) Ideal CNFETs can provide significant energy and performance benefits o...