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169
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DATE
1998
IEEE
15 years 11 months ago
1998
IEEE
This paper presents a zero-skew gated clock routing technique for VLSI circuits. The gated clock tree has masking gates at the internal nodes of the clock tree, which are selectiv...
168
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ISSS
1998
IEEE
15 years 11 months ago
1998
IEEE
With the decreasing feature sizes during VLSI fabrication and the dominance of interconnect delay over that of gates, control logic and wiring no longer have a negligible impact o...
151
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ITC
1998
IEEE
15 years 11 months ago
1998
IEEE
Previously-proposed strategies for VLSI fault diagnosis have su ered from a variety of self-imposed limitations. Some techniques are limited to a speci c fault model, and many wil...
145
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ITC
1997
IEEE
15 years 11 months ago
1997
IEEE
As the sizes of general and special purpose processors increase rapidly, generating high quality manufacturing tests for them is becoming a serious problem in industry. This paper...
174
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ICCAD
1996
IEEE
15 years 11 months ago
1996
IEEE
State justification is a time-consuming operation in test generation for sequential circuits. In this paper, we present a technique to rapidly identify state elements (flip-flops)...