2778 search results - page 332 / 556 » Reuse Technique in Hardware Design |
175
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ISQED
2005
IEEE
16 years 8 days ago
2005
IEEE
In this paper, design and measurement results of a test chip that intends to evaluate differences between layout techniques for rectangular unit-capacitor arrays are introduced. P...
165
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DATE
2003
IEEE
15 years 12 months ago
2003
IEEE
The architectural study of wireless communication systems typically requires simulations with high-level models for different analog and RF blocks. Among these blocks, frequency-t...
151
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DATE
2010
IEEE
15 years 11 months ago
2010
IEEE
— To overcome issues originating from the CMOS technology, a large-scale reconfigurable data-path (LSRDP) processor based on single-flux quantum circuits is introduced. LSRDP is ...
170
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DATE
2002
IEEE
15 years 11 months ago
2002
IEEE
: A new technique is presented in this paper to improve the efficiency of data scheduling for multi-context reconfigurable architectures targeting multimedia and DSP applications. ...
126
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DSD
2002
IEEE
15 years 11 months ago
2002
IEEE
In this paper we introduce concepts of a potential fault latency and a real fault latency for Finite State Machines (FSMs). The potential latency defines a minimal value of the po...