Sciweavers

2778 search results - page 331 / 556
» Reuse Technique in Hardware Design
Sort
View
DATE
2006
IEEE
94views Hardware» more  DATE 2006»
16 years 23 days ago
Procrastinating voltage scheduling with discrete frequency sets
This paper presents an efficient method to find the optimal intra-task voltage/frequency scheduling for single tasks in practical real-time systems using statistical workload in...
Zhijian Lu, Yan Zhang, Mircea R. Stan, John Lach, ...
DATE
2006
IEEE
104views Hardware» more  DATE 2006»
16 years 23 days ago
Optimizing sequential cycles through Shannon decomposition and retiming
—Optimizing sequential cycles is essential for many types of high-performance circuits, such as pipelines for packet processing. Retiming is a powerful technique for speeding pip...
Cristian Soviani, Olivier Tardieu, Stephen A. Edwa...
DATE
2006
IEEE
112views Hardware» more  DATE 2006»
16 years 23 days ago
Simultaneously improving code size, performance, and energy in embedded processors
Code size and energy consumption are critical design concerns for embedded processors as they determine the cost of the overall system. Techniques such as reduced length instructi...
Ahmad Zmily, Christos Kozyrakis
234
Voted
VALUETOOLS
2006
ACM
236views Hardware» more  VALUETOOLS 2006»
16 years 19 days ago
The DISCO network calculator: a toolbox for worst case analysis
In this paper we describe the design, implementation, and analytical background of the DISCO Network Calculator. The DISCO Network Calculator is an open-source toolbox written in ...
Jens B. Schmitt, Frank A. Zdarsky
ISCA
2005
IEEE
115views Hardware» more  ISCA 2005»
16 years 8 days ago
The V-Way Cache: Demand Based Associativity via Global Replacement
As processor speeds increase and memory latency becomes more critical, intelligent design and management of secondary caches becomes increasingly important. The efficiency of curr...
Moinuddin K. Qureshi, David Thompson, Yale N. Patt