2778 search results - page 329 / 556 » Reuse Technique in Hardware Design |
185
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DDECS
2008
IEEE
16 years 1 months ago
2008
IEEE
Abstract—In Network-on-Chip (NoC) application design, coreto-node mapping is an important but intractable optimization problem. In the paper, we use simulated annealing to tackle...
154
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ISCAS
2008
IEEE
16 years 1 months ago
2008
IEEE
—In this paper, an improved method of power control is introduced to widen the range of output power with high efficiency. Two CMOS class-E power amplifiers (PA) with different o...
155
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ISCAS
2008
IEEE
16 years 1 months ago
2008
IEEE
—A new 2xVDD-tolerant crystal oscillator circuit realized with 1xVDD CMOS devices without suffering gateoxide reliability issue is proposed, which is one of the key mixedvoltage ...
127
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ISCAS
2008
IEEE
16 years 1 months ago
2008
IEEE
— This article explores the effect of using source follower buffers (SFB) at the output of source coupled logic (SCL) circuits. This technique can help to improve the power-delay...
156
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DATE
2007
IEEE
16 years 1 months ago
2007
IEEE
— System-on-Chip designs often have a large number of timing domains. Communication between these domains requires synchronization, and the failure probabilities of these synchro...