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» Reuse Technique in Hardware Design
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CODES
2006
IEEE
16 years 22 days ago
A formal approach to robustness maximization of complex heterogeneous embedded systems
Embedded system optimization typically considers objectives such as cost, timing, buffer sizes and power consumption. Robustness criteria, i.e. sensitivity of the system to variat...
Arne Hamann, Razvan Racu, Rolf Ernst
DAC
2011
ACM
14 years 6 months ago
AENEID: a generic lithography-friendly detailed router based on post-RET data learning and hotspot detection
In the era of deep sub-wavelength lithography for nanometer VLSI designs, manufacturability and yield issues are critical and need to be addressed during the key physical design i...
Duo Ding, Jhih-Rong Gao, Kun Yuan, David Z. Pan
DAC
2006
ACM
16 years 7 months ago
Synthesis of high-performance packet processing pipelines
Packet editing is a fundamental building block of data communication systems such as switches and routers. Circuits that implement this function are critical and define the featur...
Cristian Soviani, Ilija Hadzic, Stephen A. Edwards
ASPDAC
2006
ACM
114views Hardware» more  ASPDAC 2006»
16 years 19 days ago
High level equivalence symmetric input identification
Symmetric input identification is an important technique in logic synthesis. Previous approaches deal with this problem by building BDDs and developing algorithms to determine symm...
Ming-Hong Su, Chun-Yao Wang
DFT
2005
IEEE
72views VLSI» more  DFT 2005»
16 years 8 days ago
Soft Error Modeling and Protection for Sequential Elements
Sequential elements, flip-flops, latches, and memory cells, are the most vulnerable components to soft errors. Since state-of-the-art designs contain millions of bistables, it i...
Hossein Asadi, Mehdi Baradaran Tahoori