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ICCD
2007
IEEE
206views Hardware» more  ICCD 2007»
16 years 3 months ago
SCAFFI: An intrachip FPGA asynchronous interface based on hard macros
Building fully synchronous VLSI circuits is becoming less viable as circuit geometries evolve. However, before the adoption of purely asynchronous strategies in VLSI design, globa...
Julian J. H. Pontes, Rafael Soares, Ewerson Carval...
ICCAD
2005
IEEE
98views Hardware» more  ICCAD 2005»
16 years 3 months ago
Clustering for processing rate optimization
Clustering (or partitioning) is a crucial step between logic synthesis and physical design in the layout of a large scale design. A design verified at the logic synthesis level m...
Chuan Lin, Jia Wang, Hai Zhou
ISLPED
2009
ACM
110views Hardware» more  ISLPED 2009»
16 years 1 months ago
SOI, interconnect, package, and mainboard thermal characterization
This paper presents an evaluation to determine the importance of the accurate thermal characterization for several elements of a semiconductor device. Specifically, it evaluates ...
Joseph Nayfach-Battilana, Jose Renau
DATE
2008
IEEE
113views Hardware» more  DATE 2008»
16 years 1 months ago
Random Stimulus Generation using Entropy and XOR Constraints
Despite the growing research effort in formal verification, constraint-based random simulation remains an integral part of design validation, especially for large design componen...
Stephen Plaza, Igor L. Markov, Valeria Bertacco
CODES
2007
IEEE
16 years 1 months ago
Embedded software development on top of transaction-level models
Early embedded SW development with transaction-level models has been broadly promoted to improve SoC design productivity. But the proposed APIs only provide low-level read/write o...
Wolfgang Klingauf, Robert Günzel, Christian S...