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ISCA
1996
IEEE
102views Hardware» more  ISCA 1996»
15 years 10 months ago
Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor
Simultaneous multithreading is a technique that permits multiple independent threads to issue multiple instructions each cycle. In previous work we demonstrated the performance po...
Dean M. Tullsen, Susan J. Eggers, Joel S. Emer, He...
MICRO
1994
IEEE
85views Hardware» more  MICRO 1994»
15 years 10 months ago
A high-performance microarchitecture with hardware-programmable functional units
This paper explores a novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications. Throu...
Rahul Razdan, Michael D. Smith
IJVR
2007
202views more  IJVR 2007»
15 years 6 months ago
Full Solid Angle Panoramic Viewing by Depth Image Warping on Field Programmable Gate Array
—To construct 3D virtual scenes from two-dimensional images with depth information, image warping techniques could be used. In this paper, a novel approach of cylindrical depth i...
Xiaoying Li, Baoquan Liu, Enhua Wu
ACSD
2010
IEEE
219views Hardware» more  ACSD 2010»
15 years 4 months ago
The Model Checking View to Clock Gating and Operand Isolation
Abstract--Clock gating and operand isolation are two techniques to reduce the power consumption in state-of-the-art hardware designs. Both approaches basically follow a two-step pr...
Jens Brandt, Klaus Schneider, Sumit Ahuja, Sandeep...
DAC
2006
ACM
16 years 7 months ago
An efficient and versatile scheduling algorithm based on SDC formulation
Scheduling plays a central role in the behavioral synthesis process, which automatically compiles high-level specifications into optimized hardware implementations. However, most ...
Jason Cong, Zhiru Zhang