2778 search results - page 311 / 556 » Reuse Technique in Hardware Design |
143
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FPL
2007
Springer
16 years 24 days ago
2007
Springer
The programmable clock networks in FPGAs have a significant impact on overall power, area, and delay. Not only does the clock network itself dissipate a significant amount of powe...
161
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CEC
2005
IEEE
16 years 8 days ago
2005
IEEE
Described are new approaches for evaluating computer program representations for use in automated search methodologies such as the evolutionary design of software. Previously, prog...
179
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DATE
2010
IEEE
15 years 11 months ago
2010
IEEE
—We present a new technique for statistical static timing analysis (SSTA) based on Markov chain Monte Carlo (MCMC), that allows fast and accurate estimation of the right-hand tai...
143
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VTS
2000
IEEE
15 years 11 months ago
2000
IEEE
1 At-speed testing is becoming increasingly difficult with external testers as the speed of microprocessors approaches the GHz range. One solution to this problem is built-in self-...
181
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CHARME
2005
Springer
15 years 8 months ago
2005
Springer
Abstract. Automatic formal verification techniques generally require exponential resources with respect to the number of primary inputs of a netlist. In this paper, we present sev...