2778 search results - page 308 / 556 » Reuse Technique in Hardware Design |
165
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MICRO
2009
IEEE
16 years 1 months ago
2009
IEEE
Efficient memory hierarchy design is critical due to the increasing gap between the speed of the processors and the memory. One of the sources of inefficiency in current caches is...
182
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ISQED
2007
IEEE
16 years 28 days ago
2007
IEEE
— In the past, dynamic voltage and frequency scaling (DVFS) has been widely used for power and energy optimization in embedded system design. As thermal issues become increasingl...
149
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ISQED
2006
IEEE
16 years 20 days ago
2006
IEEE
Gate-length biasing is a runtime leakage reduction technique that leverages on the short-channel effect by marginally increasing the gate-length of MOS devices to significantly ...
188
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DATE
2004
IEEE
15 years 10 months ago
2004
IEEE
Formal verification techniques have been playing an important role in pre-silicon validation processes. One of the most important points considered in performing formal verificati...
183
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DSS
2008
15 years 6 months ago
2008
The creation and deployment of knowledge repositories for managing, sharing, and reusing tacit knowledge within an organization has emerged as a prevalent approach in current know...