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» Reuse Technique in Hardware Design
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DATE
2007
IEEE
100views Hardware» more  DATE 2007»
16 years 29 days ago
Working with process variation aware caches
Deep-submicron designs have to take care of process variation effects as variations in critical process parameters result in large variations in access latencies of hardware compo...
Madhu Mutyam, Narayanan Vijaykrishnan
PPOPP
1990
ACM
15 years 10 months ago
Employing Register Channels for the Exploitation of Instruction Level Parallelism
Abstract - A multiprocessor system capable of exploiting fine-grained parallelism must support efficient synchronization and data passing mechanisms. This paper demonstrates the us...
Rajiv Gupta
DAC
2005
ACM
16 years 7 months ago
Diffusion-based placement migration
Placement migration is the movement of cells within an existing placement to address a variety of post-placement design closure issues, such as timing, routing congestion, signal ...
Haoxing Ren, David Zhigang Pan, Charles J. Alpert,...
CODES
2007
IEEE
16 years 1 months ago
Secure FPGA circuits using controlled placement and routing
In current Field-Programmable-Logic Architecture (FPGA) design flows, it is very hard to control the routing of submodules. It is thus very hard to make an identical copy of an ex...
Pengyuan Yu, Patrick Schaumont
ICCD
2006
IEEE
140views Hardware» more  ICCD 2006»
16 years 3 months ago
Clustering-Based Microcode Compression
Abstract— Microcode enables programmability of (micro) architectural structures to enhance functionality and to apply patches to an existing design. As more features get added to...
Edson Borin, Mauricio Breternitz Jr., Youfeng Wu, ...