2778 search results - page 305 / 556 » Reuse Technique in Hardware Design |
153
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ICCAD
2003
IEEE
16 years 3 months ago
2003
IEEE
Static timing analysis is a critical step in design of any digital integrated circuit. Technology and design trends have led to significant increase in environmental and process v...
193
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DATE
2008
IEEE
16 years 1 months ago
2008
IEEE
This paper presents a novel cycle-approximate performance estimation technique for automatically generated transaction level models (TLMs) for heterogeneous multicore designs. The...
145
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ISCAS
2008
IEEE
16 years 1 months ago
2008
IEEE
—This paper presents three techniques to reduce the power consumption in ternary content-addressable memories (TCAMs). The first technique is to use newly developed monolithical...
161
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ISCAS
2008
IEEE
16 years 1 months ago
2008
IEEE
—In this paper, an energy-efficient and high performance ternary content addressable memory (TCAM) are presented. It employs the concept of “green” microarchitecture and circ...
150
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MICRO
2008
IEEE
16 years 1 months ago
2008
IEEE
Parameter variation in integrated circuits causes sections of a chip to be slower than others. If, to prevent any resulting timing errors, we design processors for worst-case para...