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» Reuse Technique in Hardware Design
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ISQED
2006
IEEE
116views Hardware» more  ISQED 2006»
16 years 19 days ago
Probabilistic Delay Budgeting for Soft Realtime Applications
Unlike their hard realtime counterparts, soft realtime applications are only expected to guarantee their ”expected delay” over input data space. This paradigm shift calls for ...
Soheil Ghiasi, Po-Kuan Huang
190
Voted
FPGA
2006
ACM
131views FPGA» more  FPGA 2006»
15 years 10 months ago
Yield enhancements of design-specific FPGAs
The high unit cost of FPGA devices often deters their use beyond the prototyping stage. Efforts have been made to reduce the part-cost of FPGA devices, resulting in the developmen...
Nicola Campregher, Peter Y. K. Cheung, George A. C...
ETS
2011
IEEE
224views Hardware» more  ETS 2011»
14 years 6 months ago
AVF Analysis Acceleration via Hierarchical Fault Pruning
—The notion of Architectural Vulnerability Factor (AVF) has been extensively used by designers to evaluate various aspects of design robustness. While AVF is a very accurate way ...
Michail Maniatakos, Chandra Tirumurti, Abhijit Jas...
ICCD
2007
IEEE
212views Hardware» more  ICCD 2007»
16 years 3 months ago
Analytical thermal placement for VLSI lifetime improvement and minimum performance variation
DSM and nanometer VLSI designs are subject to an increasingly significant thermal effect on VLSI circuit lifetime and performance variation, which can be effectively subdued by V...
Andrew B. Kahng, Sung-Mo Kang, Wei Li, Bao Liu
ICCAD
2006
IEEE
111views Hardware» more  ICCAD 2006»
16 years 3 months ago
Mapping arbitrary logic functions into synchronous embedded memories for area reduction on FPGAs
This work describes a new mapping technique, RAM-MAP, that identifies parts of circuits that can be efficiently mapped into the synchronous embedded memories found on field prog...
Gordon R. Chiu, Deshanand P. Singh, Valavan Manoha...