2778 search results - page 302 / 556 » Reuse Technique in Hardware Design |
170
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DSD
2010
IEEE
15 years 6 months ago
2010
IEEE
—Periodic on-chip scan-based tests have to be applied to a many-core processor SoC to improve its dependability. An infrastructural IP module has been designed and incorporated i...
208
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LCTRTS
2010
Springer
15 years 4 months ago
2010
Springer
Chip multiprocessors (CMPs) are expected to be the building blocks for future computer systems. While architecting these emerging CMPs is a challenging problem on its own, program...
196
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MICRO
2006
IEEE
16 years 19 days ago
2006
IEEE
Designing and optimizing high performance microprocessors is an increasingly difficult task due to the size and complexity of the processor design space, high cost of detailed si...
198
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DAC
2006
ACM
16 years 7 months ago
2006
ACM
Ever-growing complexity is forcing design to move above RTL. For example, golden functional models are being written as clearly as possible in software and not optimized or intend...
164
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ISPD
2010
ACM
16 years 1 months ago
2010
ACM
This paper presents SafeChoice (SC), a novel clustering algorithm for wirelength-driven placement. Unlike all previous approaches, SC is proposed based on a fundamental theorem, s...