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» Reuse Technique in Hardware Design
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ISLPED
1995
ACM
116views Hardware» more  ISLPED 1995»
15 years 10 months ago
Activity-sensitive architectural power analysis for the control path
Prompted by demands for portability and low-cost packaging, the electronics industry has begun to view power consumption as a critical design criteria. As such there is a growing ...
Paul E. Landman, Jan M. Rabaey
ASPDAC
2005
ACM
104views Hardware» more  ASPDAC 2005»
15 years 8 months ago
Skew scheduling and clock routing for improved tolerance to process variations
The synthesis of clock network in the presence of process variation is becoming a vital design issue towards the performance of digital circuits. In this paper, we propose a clock ...
Ganesh Venkataraman, Cliff C. N. Sze, Jiang Hu
CG
2006
Springer
15 years 6 months ago
A realtime immersive application with realistic lighting: The Parthenon
Off-line rendering techniques have nowadays reached an astonishing level of realism but pay the cost of long computational times. The new generation of programmable graphic hardwa...
Marco Callieri, Paul E. Debevec, J. Pair, Roberto ...
CLEIEJ
2006
126views more  CLEIEJ 2006»
15 years 6 months ago
Software Based Fault Tolerance against Byzantine Failures
The proposed software technique is a very low cost and an effective solution towards designing Byzantine fault tolerant computing application systems that are not so safety critic...
Goutam Kumar Saha
ASPDAC
2012
ACM
290views Hardware» more  ASPDAC 2012»
14 years 2 months ago
CODA: A concurrent online delay measurement architecture for critical paths
With technology scaling, integrated circuits behave more unpredictably due to process variation, environmental changes and aging effects. Various variation-aware and adaptive desi...
Yubin Zhang, Haile Yu, Qiang Xu