2778 search results - page 297 / 556 » Reuse Technique in Hardware Design |
155
click to vote
ICCAD
1996
IEEE
15 years 10 months ago
1996
IEEE
In a constraint-drivenlayout synthesisenvironment,parasitic constraints are generated and implemented in each phase of the design process to meet a given set of performance specif...
160
click to vote
ICCAD
1996
IEEE
15 years 10 months ago
1996
IEEE
While numerous power optimization techniques have been at all levels of design process abstractions for electronic components, until now, power minimization in mixed mechanical-el...
142
click to vote
ITC
1996
IEEE
15 years 10 months ago
1996
IEEE
A 25k gate Test Chip was designed and manufactured to evaluate different test methods for scan-designed circuits. The design of the chip, the experiment, and preliminary experimen...
180
click to vote
ASAP
2004
IEEE
15 years 10 months ago
2004
IEEE
In this paper, we present a modular co-synthesis framework called CHARMED that solves the problem of hardware-software co-synthesis of periodic, multi-mode, distributed, embedded ...
166
click to vote
ASPDAC
2006
ACM
15 years 10 months ago
2006
ACM
Abstract-- Shrinking process geometries and frequency scaling give rise to an increasing number of interconnects that require multiple clock cycles. This paper explores efficient t...