Sciweavers

2778 search results - page 295 / 556
» Reuse Technique in Hardware Design
Sort
View
DATE
2003
IEEE
108views Hardware» more  DATE 2003»
15 years 12 months ago
Comparing Analytical Modeling with Simulation for Network Processors: A Case Study
Programming network processors remains an art due to the variety of different network processor architectures and due to little support to reason and explore implementations on su...
Matthias Gries, Chidamber Kulkarni, Christian Saue...
DATE
2003
IEEE
75views Hardware» more  DATE 2003»
15 years 12 months ago
Self-Testing Embedded Checkers for Bose-Lin, Bose, and a Class of Borden Codes
—A new approach for designing t-UED and BUED code checkers is presented. In particular we consider Borden codes for t = 2k − 1, Bose and Bose-Lin codes. The design technique fo...
Steffen Tarnick
ISQED
2003
IEEE
121views Hardware» more  ISQED 2003»
15 years 12 months ago
Monolithic DC-DC Converter Analysis And Mosfet Gate Voltage Optimization
— The design of an efficient monolithic buck converter is presented in this paper. A low swing MOSFET gate drive technique is proposed that improves the efficiency characteristic...
Volkan Kursun, Siva Narendra, Vivek De, Eby G. Fri...
ITC
2003
IEEE
123views Hardware» more  ITC 2003»
15 years 12 months ago
A Comprehensive Approach to Assessing and Analyzing 1149.1 Test Logic
In this paper we introduce a tool which is capable of verifying an 1149.1 test logic implementation and its compliance to the IEEE 1149.1 Standard [1][2] while providing a precise...
Kevin Melocco, Hina Arora, Paul Setlak, Gary Kunse...
ITC
2003
IEEE
205views Hardware» more  ITC 2003»
15 years 12 months ago
H-DFT: A Hybrid DFT Architecture For Low-Cost High Quality Structural Testing
This paper describes a Hybrid DFT (H-DFT) architecture for low-cost, high quality structural testing in the high volume manufacturing (HVM) environment. This structure efficiently...
David M. Wu, Mike Lin, Subhasish Mitra, Kee Sup Ki...