2778 search results - page 290 / 556 » Reuse Technique in Hardware Design |
207
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DATE
2002
IEEE
15 years 11 months ago
2002
IEEE
In this paper we propose a new compression algorithm geared to reduce the time needed to test scan-based designs. Our scheme compresses the test vector set by encoding the bits th...
148
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SIGMETRICS
1998
ACM
15 years 10 months ago
1998
ACM
This paper presents cooperative prefetching and caching — the use of network-wide global resources (memories, CPUs, and disks) to support prefetching and caching in the presence...
148
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ISLPED
1995
ACM
15 years 10 months ago
1995
ACM
We argue that the clocked-CMOS (C2MOS) circuit family provides a very high throughput and low power alternative to other existing circuit techniques for the fast developing market...
180
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CODES
2007
IEEE
16 years 29 days ago
2007
IEEE
As an emerging technology, sensor networks provide the ability to accurately monitor the characteristics of wide geographical areas over long periods of time. The lifetime of indi...
158
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ICCAD
2007
IEEE
16 years 28 days ago
2007
IEEE
—In latency-insensitive design shell modules are used to encapsulate system components (pearls) in order to interface them with the given latency-insensitive protocol and dynamic...