2778 search results - page 289 / 556 » Reuse Technique in Hardware Design |
147
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ASPDAC
2009
ACM
16 years 1 months ago
2009
ACM
—In network-on-chip, computing worst-case delay bound for packet delivery is crucial for designing predictable systems but yet an intractable problem due to complicated resource ...
157
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ISLPED
2009
ACM
16 years 1 months ago
2009
ACM
Emerging organic light-emitting diode (OLED)-based displays have drastically different power consumption when displaying different colors, due to their emissive nature. They bring...
161
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DATE
2008
IEEE
16 years 1 months ago
2008
IEEE
Run-time reconfigurable logic is a very attractive alterative in the design of SoC. However, configuration overhead can largely decrease the system performance. In this work, we p...
166
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DDECS
2008
IEEE
16 years 1 months ago
2008
IEEE
— Due to ever increasing design sizes more efficient tools for Automatic Test Pattern Generation (ATPG) are needed. Recently ATPG based on Boolean satisfiability (SAT) has been ...
142
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DATE
2007
IEEE
16 years 29 days ago
2007
IEEE
We present an algorithm to automatically design posynomial models for parameters of the MOS transistors using simulation data. These models improve the accuracy of the Geometric P...