2778 search results - page 288 / 556 » Reuse Technique in Hardware Design |
172
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ICCAD
2005
IEEE
16 years 3 months ago
2005
IEEE
Based on a timing yield model, a statistical static timing analysis technique is proposed. This technique preserves existing methodology by selecting a “device file setting” ...
189
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ICCAD
2002
IEEE
16 years 3 months ago
2002
IEEE
This paper describes an optimization technique able to optimize a complete wireless receiver architecture in a reasonable amount of time. The optimizer alternates between spice le...
152
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ICCAD
2001
IEEE
16 years 3 months ago
2001
IEEE
Retiming is a widely investigated technique for performance optimization. It performs powerful modifications on a circuit netlist. However, often it is not clear, whether the pred...
151
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DATE
2009
IEEE
16 years 1 months ago
2009
IEEE
—Today verification, testing and debugging of SystemC models can be applied at an early stage in the design process. To support these techniques gaining required information of ...
168
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DDECS
2009
IEEE
16 years 1 months ago
2009
IEEE
—Automatic Test Pattern Generation (ATPG) based on Boolean satisfiability (SAT) has been shown to be a beneficial complement to traditional ATPG techniques. Boolean solvers wor...