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DAC
2007
ACM
16 years 7 months ago
Global Critical Path: A Tool for System-Level Timing Analysis
An effective method for focusing optimization effort on the most important parts of a design is to examine those elements on the critical path. Traditionally, the critical path is...
Girish Venkataramani, Mihai Budiu, Tiberiu Chelcea...
WISER
2004
ACM
16 years 21 hour ago
Hardware/software co-design for power system test development
Many hardware/software co-design models have been proposed [7, 2, 5, 6] that attempt to address problems in the hardware/software interface, in partitioning the system between har...
Austin Armbruster, Matt Ryan, Xiaoqing Frank Liu, ...
ICCAD
2001
IEEE
86views Hardware» more  ICCAD 2001»
16 years 3 months ago
System-Level Exploration for Pareto-Optimal Configurations in Parameterized Systems-on-a-Chip
In this work, we provide a technique for efficiently exploring the configuration space of a parameterized system-on-a-chip (SOC) architecture to find all Pareto-optimal configurat...
Tony Givargis, Frank Vahid, Jörg Henkel
DATE
2002
IEEE
73views Hardware» more  DATE 2002»
15 years 11 months ago
A Burst-Mode Oriented Back-End for the Balsa Synthesis System
This paper introduces several new component clustering techniques for the optimization of asynchronous systems. In particular, novel “Burst-Mode aware” restrictions are impose...
Tiberiu Chelcea, Steven M. Nowick, Andrew Bardsley...
DATE
2000
IEEE
65views Hardware» more  DATE 2000»
15 years 11 months ago
Test Quality and Fault Risk in Digital Filter Datapath BIST
An objective of DSP testing should be to ensure that any errors due to missed faults are infrequent compared to a circuit’s intrinsic errors, such as overflow. A method is prop...
Laurence Goodby, Alex Orailoglu