2778 search results - page 279 / 556 » Reuse Technique in Hardware Design |
172
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DATE
2008
IEEE
16 years 1 months ago
2008
IEEE
Retargetable C compilers are key components of today’s embedded processor design platforms for quickly obtaining compiler support and performing early processor architecture exp...
186
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ICCAD
1997
IEEE
15 years 10 months ago
1997
IEEE
Traditional synthesis techniques optimize CMOS circuits in two phases i) logic minimization and ii) library mapping phase. Typically, the structures and the sizes of the gates in ...
157
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ICCAD
2009
IEEE
15 years 4 months ago
2009
IEEE
Traditional circuit design focuses on optimizing the static critical paths no matter how infrequently these paths are exercised dynamically. Circuit optimization is then tuned to ...
192
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DAC
2010
ACM
15 years 1 months ago
2010
ACM
This paper presents a logic restructuring technique named node addition and removal (NAR). It works by adding a node into a circuit to replace an existing node and then removing t...
143
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GLVLSI
2009
IEEE
16 years 1 months ago
2009
IEEE
Logic decomposition has been extensively used to optimize the worst-case delay and the area in the technology independent phase. Bi-decomposition is one of the state-of-art techni...