Sciweavers

2778 search results - page 278 / 556
» Reuse Technique in Hardware Design
Sort
View
ISSS
2000
IEEE
91views Hardware» more  ISSS 2000»
15 years 11 months ago
Instruction-based System-level Power Evaluation of System-On-A-Chip Peripheral Cores
Various system-level core-based power evaluation approaches for core types like microprocessors, caches, main memories, and buses, have been proposed in the past. Approaches for o...
Tony Givargis, Frank Vahid, Jörg Henkel
CODES
1996
IEEE
15 years 10 months ago
Uninterpreted Co-Simulation for Performance Evaluation of Hw/Sw Systems
Performance modeling and evaluation of embedded hardware/software systems is important to help the CoDesign process. The hardware/software partitioning needs to be evaluated befor...
Jean Paul Calvez, Dominique Heller, Olivier Pasqui...
ASPDAC
2006
ACM
176views Hardware» more  ASPDAC 2006»
16 years 17 days ago
Conversion of reference C code to dataflow model: H.264 encoder case study
– Model-based design is widely accepted in developing complex embedded system under intense time-to-market pressure. While it promises improved design productivity, the main bott...
Hyeyoung Hwang, Taewook Oh, Hyunuk Jung, Soonhoi H...
ISLPED
2005
ACM
123views Hardware» more  ISLPED 2005»
16 years 4 days ago
Coordinated, distributed, formal energy management of chip multiprocessors
Designers are moving toward chip-multiprocessors (CMPs) to leverage application parallelism for higher performance while keeping design complexity under control. However, to date,...
Philo Juang, Qiang Wu, Li-Shiuan Peh, Margaret Mar...
DAC
2001
ACM
16 years 7 months ago
Watermarking of SAT using Combinatorial Isolation Lemmas
Watermarking of hardware and software designs is an effective mechanism for intellectual property protection (IPP). Two important criteria for watermarking schemes are credibility...
Rupak Majumdar, Jennifer L. Wong