2778 search results - page 274 / 556 » Reuse Technique in Hardware Design |
219
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ITC
1997
IEEE
15 years 10 months ago
1997
IEEE
This paper presents a new approach for designing test sequences to be generated on–chip. The proposed technique is based on machine learning, and provides a way to generate effi...
154
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ASPLOS
2008
ACM
15 years 8 months ago
2008
ACM
Nested paging is a hardware solution for alleviating the software memory management overhead imposed by system virtualization. Nested paging complements existing page walk hardwar...
160
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ACSD
2005
IEEE
16 years 6 days ago
2005
IEEE
Register Transfer Level (RTL) synthesis model which simplified the design of clocked circuits allowed design automation boost and VLSI progress for more than a decade. Shrinking t...
151
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DATE
2010
IEEE
15 years 11 months ago
2010
IEEE
—This paper proposes a circuit optimization approach that can ease the computational burden on the simulation-based circuit optimizers by leveraging simple design equations that ...
250
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ASPDAC
2006
ACM
16 years 17 days ago
2006
ACM
With shrinking technology, the timing variation of a digital circuit is becoming the most important factor while designing a functionally reliable circuit. Gate sizing has emerged...