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TVLSI
2008
108views more  TVLSI 2008»
15 years 6 months ago
Unified Convolutional/Turbo Decoder Design Using Tile-Based Timing Analysis of VA/MAP Kernel
To satisfy the advanced forward-error-correction (FEC) standards, in which the Convolutional code and Turbo code may co-exit, a prototype design of a unified Convolutional/Turbo de...
Fan-Min Li, Cheng-Hung Lin, An-Yeu Wu
DLOG
2010
15 years 4 months ago
TBox Classification in Parallel: Design and First Evaluation
Abstract. One of the most frequently used inference services of description logic reasoners classifies all named classes of OWL ontologies into a subsumption hierarchy. Due to emer...
Mina Aslani, Volker Haarslev
ANCS
2009
ACM
15 years 4 months ago
Design of a scalable nanophotonic interconnect for future multicores
As communication-centric computing paradigm gathers momentum due to increased wire delays and excess power dissipation with technology scaling, researchers have focused their atte...
Avinash Karanth Kodi, Randy Morris
DATE
2008
IEEE
143views Hardware» more  DATE 2008»
16 years 1 months ago
Comparison of Opamp-Based and Comparator-Based Delta-Sigma Modulation
Comparator-based switched capacitor (CBSC) circuits present an alternative approach to designing sampled data systems based on the principle of detecting a virtual ground conditio...
Massoud Momeni, Petru Bogdan Bacinschi, Manfred Gl...
IESS
2009
Springer
182views Hardware» more  IESS 2009»
15 years 4 months ago
Modeling Cache Effects at the Transaction Level
Abstract. Embedded system design complexities are growing exponentially. Demand has increased for modeling techniques that can provide both accurate measurements of delay and fast ...
Ardavan Pedram, David Craven, Andreas Gerstlauer