2778 search results - page 268 / 556 » Reuse Technique in Hardware Design |
157
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IOLTS
2003
IEEE
15 years 12 months ago
2003
IEEE
Fault tolerant design is a technique emerging in Integrated Circuits (IC’s) to deal with the increasing error susceptibility (Soft Errors, or Single Event Upsets, SEU) caused by...
211
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CASES
2008
ACM
15 years 8 months ago
2008
ACM
We introduce the first approach that can actively control multiple hardware intellectual property (IP) cores used in an integrated circuit (IC). The IP rights owner(s) can remotel...
175
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FPL
2005
Springer
16 years 3 days ago
2005
Springer
String pattern matching is a computationally expensive task, and when implemented in hardware, it can consume a large amount of resources for processing and storage. This paper pr...
189
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ATS
2010
IEEE
15 years 1 months ago
2010
IEEE
In recent technology nodes, reliability is considered a part of the standard design flow at all levels of embedded system design. While techniques that use only low-level models at...
195
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DELTA
2010
IEEE
15 years 11 months ago
2010
IEEE
— FPGAs, (Field-Programmable Gate Arrays) are often used for embedded image processing applications. Parallelism, and in particular pipelining, is the most suitable architecture ...