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DATE
2009
IEEE
141views Hardware» more  DATE 2009»
15 years 10 months ago
Evaluation on FPGA of triple rail logic robustness against DPA and DEMA
Side channel attacks are known to be efficient techniques to retrieve secret data. In this context, this paper concerns the evaluation of the robustness of triple rail logic agains...
Victor Lomné, Philippe Maurine, Lionel Torr...
ETS
2006
IEEE
89views Hardware» more  ETS 2006»
15 years 10 months ago
On-Chip Time Measurement Architecture with Femtosecond Timing Resolution
This paper presents a new on-chip time measurement architecture which is based on the Timeto-Digital Conversion (TDC) method that is capable of achieving a timing resolution of te...
Matthew Collins, Bashir M. Al-Hashimi
ISSS
1997
IEEE
128views Hardware» more  ISSS 1997»
15 years 10 months ago
Architectural Exploration and Optimization of Local Memory in Embedded Systems
Embedded processor-based systems allow for the tailoring of the on-chip memory architecture based on application-specific requirements. We present an analytical strategy for explo...
Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nico...
ISSS
1995
IEEE
59views Hardware» more  ISSS 1995»
15 years 10 months ago
Multiple-process behavioral synthesis for mixed hardware-software systems
Systems composed of microprocessors interacting with ASICs are necessarily multiple-process systems, since the controller in the microprocessor is separate from any controllers on...
Jay K. Adams, Donald E. Thomas
TC
2002
15 years 6 months ago
Architectures and VLSI Implementations of the AES-Proposal Rijndael
Two architectures and VLSI implementations of the AES Proposal, Rijndael, are presented in this paper. These alternative architectures are operated both for encryption and decrypti...
Nicolas Sklavos, Odysseas G. Koufopavlou