2778 search results - page 262 / 556 » Reuse Technique in Hardware Design |
157
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ISSS
1998
IEEE
15 years 10 months ago
1998
IEEE
This paper presents an application-specific, heterogeneous multiprocessor synthesis system, named HeMPS, that combines a form of Evolutionary Computation known as Differential Evo...
151
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ITC
1998
IEEE
15 years 10 months ago
1998
IEEE
Automated fault diagnosis based on the stuckat fault model is not always effective. This paper presents practical experiences in applying a bridging fault based diagnosis techniqu...
172
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ICCAD
1994
IEEE
15 years 10 months ago
1994
IEEE
This work presents techniques for computing the switching activities of all circuit nodes under pseudorandom or biased input sequences and assuming a zero delay mode of operation....
126
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ISCAS
1993
IEEE
15 years 10 months ago
1993
IEEE
- A novel VLSI implementation of the Viterbi algorithm based on a cascade architecture is presented. Survivor sequence memory management is implemented using a new single read poin...
171
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ASPDAC
2007
ACM
15 years 10 months ago
2007
ACM
A new graph reduction approach to symbolic circuit analysis is developed in this paper. A Binary Decision Diagram (BDD) mechanism is formulated, together with a specially designed ...