2778 search results - page 260 / 556 » Reuse Technique in Hardware Design |
158
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ASYNC
2007
IEEE
15 years 10 months ago
2007
IEEE
Few formal verification techniques are currently available for asynchronous designs. In this paper, we describe a new approach for the formal verification of asynchronous architec...
180
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ISLPED
1995
ACM
15 years 10 months ago
1995
ACM
We will present a power estimation technique for digital integrated circuits that operates at the register transfer level RTL . Such a high-level power estimation capability is r...
176
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ICCAD
1991
IEEE
15 years 10 months ago
1991
IEEE
As feature sizes decrease and chip sizes increase, the area and performance of chips become dominated by the interconnect. In spite of this trend, most existing synthesis systems ...
173
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ISLPED
2010
ACM
15 years 5 months ago
2010
ACM
In this paper, a novel thermal-aware dynamic placement planner for reconfigurable systems is presented, which targets transient temperature reduction. Rather than solving time-...
110
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DATE
2007
IEEE
16 years 27 days ago
2007
IEEE
This paper discusses several forms of heterogeneity in systems on chip and systems in package. A means to distinguish the various forms of heterogeneity is given, with an estimati...