2778 search results - page 256 / 556 » Reuse Technique in Hardware Design |
158
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DATE
2009
IEEE
16 years 1 months ago
2009
IEEE
—Redundancy Addition and Removal (RAR) is a restructuring technique used in the synthesis and optimization of logic designs. It can remove an existing target wire and add an alte...
131
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ISCAS
2008
IEEE
16 years 29 days ago
2008
IEEE
—this paper reports a PFD/CP linearization technique and a new charge pump circuit to enhance the performance of a delta-sigma (∆Σ) fractional-N PLL. The proposed method impro...
139
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DATE
2000
IEEE
15 years 11 months ago
2000
IEEE
In this paper we address the problem of designing very high throughput finite state machines (FSMs). The presence of loops in sequential circuits prevents a straightforward and g...
170
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ICCAD
1998
IEEE
15 years 10 months ago
1998
IEEE
In this paper, we propose a new logic synthesis methodology to deal with the increasing importance of the interconnect delay in deepsubmicron technologies. We first show that conv...
163
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DATE
1997
IEEE
15 years 10 months ago
1997
IEEE
The paper proposes a novel approach in an attempt to solve the test problem for sequential circuits. Up until now, most of the classical test pattern techniques use a number of al...