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ITC
1997
IEEE
80views Hardware» more  ITC 1997»
15 years 10 months ago
Scan Synthesis for One-Hot Signals
Tri-state buses and pass transistor logic are used in many complex applications to achieve high performance and small area. Such circuits often contain logic requiring one-hot sig...
Subhasish Mitra, LaNae J. Avra, Edward J. McCluske...
ASPDAC
2010
ACM
152views Hardware» more  ASPDAC 2010»
15 years 4 months ago
Slack redistribution for graceful degradation under voltage overscaling
Modern digital IC designs have a critical operating point, or "wall of slack", that limits voltage scaling. Even with an errortolerance mechanism, scaling voltage below a...
Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, Jo...
DATE
2007
IEEE
146views Hardware» more  DATE 2007»
16 years 27 days ago
DFM/DFY: should you trust the surgeon or the family doctor?
Everybody agrees that curing DFM/DFY issues is of paramount importance at 65 nanometers and beyond. Unfortunately, there is disagreement about how and when to cure them. “Surgeo...
Marco Casale-Rossi, Andrzej J. Strojwas, Robert C....
ISCA
2000
IEEE
121views Hardware» more  ISCA 2000»
15 years 11 months ago
Selective, accurate, and timely self-invalidation using last-touch prediction
Communication in cache-coherent distributed shared memory (DSM) often requires invalidating (or writing back) cached copies of a memory block, incurring high overheads. This paper...
An-Chow Lai, Babak Falsafi
FPL
2005
Springer
122views Hardware» more  FPL 2005»
16 years 2 days ago
FPGA-Aware Garbage Collection in Java
— During codesign of a system, one still runs into the impedance mismatch between the software and hardware worlds. er identifies the different levels of abstraction of hardware...
Philippe Faes, Mark Christiaens, Dries Buytaert, D...