2778 search results - page 249 / 556 » Reuse Technique in Hardware Design |
166
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ISLPED
2003
ACM
15 years 11 months ago
2003
ACM
A new architectural technique to reduce power dissipation in data caches is proposed. In multimedia applications, a major portion of data cache accesses hit in the same cache set ...
161
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DATE
2010
IEEE
15 years 11 months ago
2010
IEEE
Carbon Nanotube Field-Effect Transistors (CNFETs) can potentially provide significant energy-delay-product benefits compared to silicon CMOS. However, CNFET circuits are subject t...
162
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ISSS
2002
IEEE
15 years 11 months ago
2002
IEEE
Fast distributed cosimulation is a challenging problem for the embedded system design. The main theme of this paper is to increase simulation speed by reducing the frequency of in...
156
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ASPDAC
2007
ACM
15 years 10 months ago
2007
ACM
The high performance requirements of networking applications has led to the advent of programmable network processor (NP) architectures that incorporate symmetric multiprocessing, ...
145
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ICCD
1995
IEEE
15 years 10 months ago
1995
IEEE
STARI is a high-speed signaling technique that uses both synchronous and self-timed circuits. To demonstrate STARI, a chip has been fabricated using the MOSIS 2 CMOS process. In a...