2778 search results - page 248 / 556 » Reuse Technique in Hardware Design |
163
click to vote
ICCAD
2001
IEEE
16 years 3 months ago
2001
IEEE
This paper presents a method to automatically generate posynomial response surface models for the performance parameters of analog integrated circuits. The posynomial models enabl...
166
click to vote
DATE
2009
IEEE
16 years 1 months ago
2009
IEEE
NBTI (Negative Bias Temperature Instability) has emerged as the dominant PMOS device failure mechanism for sub100nm VLSI designs. There is little research to quantify its impact o...
167
click to vote
DATE
2008
IEEE
16 years 1 months ago
2008
IEEE
Simulation of transaction level models (TLMs) is an established embedded systems design technique. Its use cases include virtual prototyping for early software development, platfo...
166
click to vote
SASP
2008
IEEE
16 years 28 days ago
2008
IEEE
This paper proposes an energy efficient processor which can be used as a design alternative for the dynamic voltage scaling (DVS) processors in embedded system design. The proces...
180
click to vote
ISQED
2006
IEEE
16 years 17 days ago
2006
IEEE
Due to aggressive technology scaling, VLSI circuits are becoming increasingly susceptible to transient errors caused by single-event-upsets (SEUs). In this paper, we introduce two...