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» Reuse Technique in Hardware Design
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DFT
2003
IEEE
113views VLSI» more  DFT 2003»
15 years 11 months ago
Buffer and Controller Minimisation for Time-Constrained Testing of System-On-Chip
Test scheduling and Test Access Mechanism (TAM) design are two important tasks in the development of a System-on-Chip (SOC) test solution. Previous test scheduling techniques assu...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...
ISSS
2002
IEEE
103views Hardware» more  ISSS 2002»
15 years 11 months ago
A Symbolic Approach for the Combined Solution of Scheduling and Allocation
Scheduling is widely recognized as a very important step in highlevel synthesis. Nevertheless, it is usually done without taking into account the effects on the actual hardware im...
Luciano Lavagno, Mihai T. Lazarescu, Stefano Quer,...
EGH
2004
Springer
15 years 12 months ago
Realtime ray tracing of dynamic scenes on an FPGA chip
Realtime ray tracing has recently established itself as a possible alternative to the current rasterization approach for interactive 3D graphics. However, the performance of exist...
Jörg Schmittler, Sven Woop, Daniel Wagner, Wo...
ISLPED
2006
ACM
128views Hardware» more  ISLPED 2006»
16 years 15 days ago
Design and power management of energy harvesting embedded systems
Harvesting energy from the environment is a desirable and increasingly important capability in several emerging applications of embedded systems such as sensor networks, biomedica...
Vijay Raghunathan, Pai H. Chou
DAC
2002
ACM
16 years 7 months ago
Exploiting shared scratch pad memory space in embedded multiprocessor systems
In this paper, we present a compiler strategy to optimize data accesses in regular array-intensive applications running on embedded multiprocessor environments. Specifically, we p...
Mahmut T. Kandemir, J. Ramanujam, Alok N. Choudhar...