Sciweavers

2778 search results - page 234 / 556
» Reuse Technique in Hardware Design
Sort
View
PDPTA
2004
15 years 8 months ago
Design of a Real-Time Scheduler for Kahn Process Networks on Multiprocessor Systems
High-throughput real-time systems require non-standard and costly hardware and software solutions. Modern workstation can represent a credible alternative to develop realtime inte...
Javed Dulloo, Philippe Marquet
ISLPED
2004
ACM
149views Hardware» more  ISLPED 2004»
15 years 12 months ago
Creating a power-aware structured ASIC
In an attempt to enable the cost-effective production of lowand mid-volume application-specific chips, researchers have proposed a number of so-called structured ASIC architectur...
R. Reed Taylor, Herman Schmit
ISCAS
2006
IEEE
122views Hardware» more  ISCAS 2006»
16 years 16 days ago
A new look at reversible memory elements
Abstract— Although many researchers are investigating techniques to synthesize reversible combinational logic, there is little work in the area of sequential reversible logic. We...
Jacqueline E. Rice
ISLPED
2005
ACM
72views Hardware» more  ISLPED 2005»
16 years 2 days ago
A low power current steering digital to analog converter in 0.18 Micron CMOS
This paper discusses a number of circuit techniques which address the DC and AC distortion performance of a low power current steering Digital-to-Analog Converter design. The desi...
Douglas Mercer
DATE
2007
IEEE
185views Hardware» more  DATE 2007»
16 years 26 days ago
An ILP formulation for system-level application mapping on network processor architectures
Current day network processors incorporate several architectural features including symmetric multi-processing (SMP), block multi-threading, and multiple memory elements to suppor...
Christopher Ostler, Karam S. Chatha