2778 search results - page 232 / 556 » Reuse Technique in Hardware Design |
159
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ISLPED
2005
ACM
16 years 2 days ago
2005
ACM
In this paper, we propose joint repeater insertion and crosstalk avoidance coding as a low-power alternative to repeater insertion for global bus design in nanometer technologies....
186
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CODES
2003
IEEE
15 years 11 months ago
2003
IEEE
Distributed embedded systems implemented with mixed, eventtriggered and time-triggered task sets, which communicate over bus protocols consisting of both static and dynamic phases...
192
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FPGA
2008
ACM
15 years 8 months ago
2008
ACM
Application-Specific Instruction-set Processors (ASIP) can improve execution speed by using custom instructions. Several ASIP design automation flows have been proposed recently. ...
228
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ISCA
2010
IEEE
15 years 11 months ago
2010
IEEE
This paper presents a fundamental law for parallel performance: it shows that parallel performance is not only limited by sequential code (as suggested by Amdahl’s law) but is a...
197
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TVCG
2012
13 years 9 months ago
2012
—This paper presents a 2D flow visualization user study that we conducted using new methodologies to increase the objectiveness. We evaluated grid-based variable-size arrows, eve...