2778 search results - page 231 / 556 » Reuse Technique in Hardware Design |
145
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ISCA
2000
IEEE
15 years 11 months ago
2000
IEEE
As DRAM access latencies approach a thousand instructionexecution times and on-chip caches grow to multiple megabytes, it is not clear that conventional cache structures continue ...
170
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DATE
2004
IEEE
15 years 10 months ago
2004
IEEE
In this paper, we present various challenges that arise in the delivery and exchange of multimedia information to mobile devices. Specifically, we focus on techniques for maintain...
179
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ASPDAC
2011
ACM
14 years 10 months ago
2011
ACM
- In low temperature polycrystalline silicon (LTPS) based display technologies, the electrical parameter variations in thin film transistors (TFTs) caused by random grain boundarie...
223
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IOLTS
2009
IEEE
16 years 1 months ago
2009
IEEE
— The paper deals with designing fault tolerant finite state machines (FSMs) by nanoelectronic programmable logic arrays (PLAs). Two main critical parameters of the fault toleran...
170
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GLVLSI
2005
IEEE
16 years 3 days ago
2005
IEEE
This paper addresses a pipelined partial rolling (PPR) architecture for the AES encryption. The key technique is the PPR architecture, which is suitable for FPGA implementation. U...