2778 search results - page 224 / 556 » Reuse Technique in Hardware Design |
148
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ECBS
2006
IEEE
15 years 10 months ago
2006
IEEE
We present in this paper a unified paradigm for the verification and validation of software and systems engineering design models expressed in UML 2.0 or SysML. This paradigm reli...
187
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ISLPED
2007
ACM
15 years 8 months ago
2007
ACM
This paper addresses the problem of power-optimal repeater insertion for global buses in the presence of crosstalk noise. MTCMOS technique by inserting high-Vth sleep transistors ...
197
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ASPDAC
2011
ACM
14 years 10 months ago
2011
ACM
— Code coverage is a popular method to find design bugs and verification loopholes. However, once a piece of code is determined to be unreachable, diagnosing the cause of the p...
151
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ISCA
1998
IEEE
15 years 10 months ago
1998
IEEE
Explicitly Parallel Instruction Computing (EPIC) architectures require the compiler to express program instruction level parallelism directly to the hardware. EPIC techniques whic...
188
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DAC
2005
ACM
15 years 8 months ago
2005
ACM
With 90nm CMOS in production and 65nm testing in progress, power has been pushed to the forefront of design metrics. This paper will outline practical techniques that are used to ...