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» Reuse Technique in Hardware Design
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DSD
2006
IEEE
113views Hardware» more  DSD 2006»
15 years 8 months ago
Cascade Scheme for Concurrent Errors Detection
The paper deals with synthesis technique for designing circuits with cascade errors detection. The proposed technique is based on partitioning a scheme into a number of cascades f...
Ilya Levin, Vladimir Ostrovsky, Osnat Keren, Vladi...
ASPDAC
2010
ACM
169views Hardware» more  ASPDAC 2010»
15 years 4 months ago
Adaptive performance control with embedded timing error predictive sensors for subthreshold circuits
Abstract-- This paper presents an adaptive technique for compensating manufacturing and environmental variability in subthreshold circuits using "canary flip-flop" that c...
Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyam...
DATE
2009
IEEE
79views Hardware» more  DATE 2009»
16 years 1 months ago
Solver technology for system-level to RTL equivalence checking
—Checking the equivalence of a system-level model against an RTL design is a major challenge. The reason is that usually the system-level model is written by a system architect, ...
Alfred Kölbl, Reily Jacoby, Himanshu Jain, Ca...
TVLSI
2010
15 years 1 months ago
A Low-Cost VLSI Implementation for Efficient Removal of Impulse Noise
Abstract--Image and video signals might be corrupted by impulse noise in the process of signal acquisition and transmission. In this paper, an efficient VLSI implementation for rem...
Pei-Yin Chen, Chih-Yuan Lien, Hsu-Ming Chuang
ICCAD
2006
IEEE
141views Hardware» more  ICCAD 2006»
16 years 3 months ago
A code refinement methodology for performance-improved synthesis from C
Although many recent advances have been made in hardware synthesis techniques from software programming languages such as C, the performance of synthesized hardware commonly suffe...
Greg Stitt, Frank Vahid, Walid A. Najjar