2778 search results - page 210 / 556 » Reuse Technique in Hardware Design |
150
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ASPDAC
2008
ACM
15 years 8 months ago
2008
ACM
Accurate modeling of delay, power, and area of interconnections early in the design phase is crucial for effective system-level optimization. Models presently used in system-level...
201
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ICCD
2008
IEEE
16 years 3 months ago
2008
IEEE
— Embedded processors are required to achieve high performance while running on batteries. Thus, they must exploit all the possible means available to reduce energy consumption w...
198
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ICCAD
1999
IEEE
15 years 10 months ago
1999
IEEE
Constraining and input biasing are frequently used techniques in functional verification methodologies based on randomized simulation generation. Constraints confine the simulatio...
159
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HPCA
2009
IEEE
16 years 7 months ago
2009
IEEE
Some instructions have more impact on processor performance than others. Identification of these critical instructions can be used to modify and improve instruction processing. Pr...
164
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VTS
2007
IEEE
16 years 22 days ago
2007
IEEE
—As the complexity of the integrated circuits increases, they become more susceptible to manufacturing faults, decreasing the total process yield. Thus, it would be desirable to ...