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» Reuse Technique in Hardware Design
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ASAP
2005
IEEE
121views Hardware» more  ASAP 2005»
16 years 3 days ago
Using TLM for Exploring Bus-based SoC Communication Architectures
As billion transistor System-on-chips (SoC) become commonplace and design complexity continues to increase, designers are faced with the daunting task of meeting escalating design...
Sudeep Pasricha, Mohamed Ben-Romdhane
DATE
2002
IEEE
97views Hardware» more  DATE 2002»
15 years 11 months ago
Fast Method to Include Parasitic Coupling in Circuit Simulations
S-parameter based circuit simulators are used a lot for the design of microwave circuits. The accuracy of these simulators is limited by the fact that they do not take the electro...
B. L. A. Van Thielen, G. A. E. Vandenbosch
ICECCS
2002
IEEE
106views Hardware» more  ICECCS 2002»
15 years 11 months ago
Validating Run-time Interactions in Distributed Java Applications
Distributed Java applications represent a large growth area in software. Validating such applications using information from runtime interactions is a challenge. We propose techni...
Sudipto Ghosh, Nishant Bawa, Sameer Goel, Raghu Re...
ITC
1998
IEEE
82views Hardware» more  ITC 1998»
15 years 10 months ago
A high speed and area efficient on-chip analog waveform extractor
ABSTRACT - A multiple pass A/D conversion technique is proposed for mixed-signal test applications. Only a single on-chip comparator and sample-and-hold circuit is required to digi...
Ara Hajjar, Gordon W. Roberts
DATE
2009
IEEE
168views Hardware» more  DATE 2009»
16 years 1 months ago
Selective state retention design using symbolic simulation
Abstract—Addressing both standby and active power is a major challenge in developing System-on-Chip designs for batterypowered products. Powering off sections of logic or memorie...
Ashish Darbari, Bashir M. Al-Hashimi, David Flynn,...