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» Reuse Technique in Hardware Design
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ISCAS
2007
IEEE
121views Hardware» more  ISCAS 2007»
16 years 22 days ago
Topological Placement with Multiple Symmetry Groups of Devices for Analog Layout Design
Abstract– This paper presents an improved topological algorithm for device-level analog placement with symmetry constraints. Based on the exploration of symmetric-feasible sequen...
Karthik Krishnamoorthy, Sarat C. Maruvada, Florin ...
FPL
2005
Springer
140views Hardware» more  FPL 2005»
15 years 12 months ago
A Configuration Memory Architecture for Fast Run-Time-Reconfiguration of FPGAs
This paper presents a configuration memory architecture that offers fast FPGA reconfiguration. The underlying principle behind the design is the use of fine-grained partial rec...
Usama Malik, Oliver Diessel
ICCAD
2004
IEEE
94views Hardware» more  ICCAD 2004»
16 years 3 months ago
Timing macro-modeling of IP blocks with crosstalk
With the increase of design complexities and the decrease of minimal feature sizes, IP reuse is becoming a common practice while crosstalk is becoming a critical issue that must b...
Ruiming Chen, Hai Zhou
ACMMSP
2006
ACM
232views Hardware» more  ACMMSP 2006»
16 years 13 days ago
Implicit and explicit optimizations for stencil computations
Stencil-based kernels constitute the core of many scientific applications on block-structured grids. Unfortunately, these codes achieve a low fraction of peak performance, due pr...
Shoaib Kamil, Kaushik Datta, Samuel Williams, Leon...
ICECCS
2005
IEEE
125views Hardware» more  ICECCS 2005»
16 years 2 days ago
Model Checking Live Sequence Charts
Live Sequence Charts (LSCs) are a broad extension to Message Sequence Charts (MSCs) to capture complex interobject communication rigorously. A tool support for LSCs, named PlayEng...
Jun Sun 0001, Jin Song Dong