2778 search results - page 196 / 556 » Reuse Technique in Hardware Design |
167
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DATE
2010
IEEE
15 years 11 months ago
2010
IEEE
— In this paper, we examine the impact of application task mapping on the reliability of MPSoC in the presence of single-event upsets (SEUs). We propose a novel soft erroraware d...
163
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ICCD
2003
IEEE
16 years 3 months ago
2003
IEEE
We analyze the effect of errors in branch predictors, a representative example of speculative processor subsystems, to motivate the necessity for fault tolerance in such subsystem...
178
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ICCD
2005
IEEE
16 years 2 days ago
2005
IEEE
— With the success of formal verification techniques like equivalence checking and model checking for hardware designs, there has been growing interest in applying such techniqu...
149
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ITC
2003
IEEE
15 years 11 months ago
2003
IEEE
ct This paper describes a general technique to test external memory/caches and memory interconnects using on-chip logic. Such a test methodology is expected to significantly reduc...
157
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MICRO
2002
IEEE
15 years 11 months ago
2002
IEEE
In a 64-bit processor, many of the data values actually used in computations require much narrower data-widths. In this study, we demonstrate that instruction data-widths exhibit ...