2778 search results - page 193 / 556 » Reuse Technique in Hardware Design |
164
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DATE
1999
IEEE
15 years 10 months ago
1999
IEEE
In this paper, we consider the problem of maximizing the battery life (or duration of service) in battery-powered CMOS circuits. We first show that the battery efficiency (or utili...
175
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MICRO
2003
IEEE
15 years 11 months ago
2003
IEEE
As demand for bandwidth increases in systems-on-a-chip and chip multiprocessors, networks are fast replacing buses and dedicated wires as the pervasive interconnect fabric for on-...
155
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FPL
2009
Springer
15 years 11 months ago
2009
Springer
Fast carry chains featuring dedicated adder circuitry is a distinctive feature of modern FPGAs. The carry chains bypass the general routing network and are embedded in the logic b...
161
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ISCA
1994
IEEE
15 years 10 months ago
1994
IEEE
In the near future, semiconductor technology will allow the integration of multiple processors on a chip or multichipmodule (MCM). In this paper we investigate the architecture an...
165
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ASAP
2006
IEEE
15 years 10 months ago
2006
IEEE
A popular approach to guarantee fault tolerance in safety-critical applications is to run the application on two processors. A checkpoint is inserted at the completion of the prim...