2778 search results - page 190 / 556 » Reuse Technique in Hardware Design |
110
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ICCAD
2005
IEEE
16 years 3 months ago
2005
IEEE
— The generation of arbitrary patterns and shapes at very small scales is at the heart of our effort to miniaturize circuits and is fundamental to the development of nanotechnolo...
159
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ICCAD
2003
IEEE
16 years 3 months ago
2003
IEEE
– Many embedded system designs usually impose (hard) read-time constraints on tasks. Thus, computing a tight upper bound of the worst case execution time (WCET) of a software is ...
166
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DATE
2005
IEEE
16 years 2 days ago
2005
IEEE
On-chip buses are typically designed to meet performance constraints at worst-case conditions, including process corner, temperature, IR-drop, and neighboring net switching patter...
161
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DSD
2002
IEEE
15 years 11 months ago
2002
IEEE
This paper presents a design for a low-power digital matched filter (DMF) applicable to Wideband-Code Division Multiple Access (W-CDMA), which is a Direct-Sequence Spread-Spectrum...
161
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ISQED
2007
IEEE
16 years 22 days ago
2007
IEEE
In high-level synthesis for FPGA designs, scheduling and chaining of operations for optimal performance remain challenging problems. In this paper, we present a balanced schedulin...