2778 search results - page 186 / 556 » Reuse Technique in Hardware Design |
174
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CODES
2003
IEEE
15 years 11 months ago
2003
IEEE
In this paper, we are concerned about the performance estimation of bus-based architectures assuming that the task partitioning on the processing components is already determined....
146
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ASPDAC
2008
ACM
15 years 8 months ago
2008
ACM
Continuous transistor scaling due to improvements in CMOS devices and manufacturing technologies is increasing processor power densities and temperatures; thus, creating challenges...
183
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DSD
2010
IEEE
15 years 6 months ago
2010
IEEE
—Since many embedded systems execute a predefined set of programs, tuning system components to application programs and data is the approach chosen by many design techniques to o...
168
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DATE
2009
IEEE
16 years 1 months ago
2009
IEEE
- In this paper, we present a design methodology for automatic platform generation of future heterogeneous systems where communication happens via the Network-onChip (NoC) approach...
165
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ATS
2005
IEEE
16 years 2 days ago
2005
IEEE
The need for high-performance pipelined architectures has resulted in the adoption of latch based designs with multiple, interacting clocks. For such designs, time sharing across ...