2778 search results - page 180 / 556 » Reuse Technique in Hardware Design |
147
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FPL
2007
Springer
16 years 18 days ago
2007
Springer
A temporal correlation based port combination algorithm that customizes the router design in Network-on-Chip (NoC) is proposed for reconfigurable systems in order to minimize req...
168
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CODES
2006
IEEE
16 years 14 days ago
2006
IEEE
Design of System-on-Chip (SoC) with regular mesh based Network-on-Chip (NoC) consists of mapping processing cores to routers, and routing of the traffic traces on the topology suc...
170
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VLSID
2001
IEEE
16 years 6 months ago
2001
IEEE
In this paper we describe a hardware design method for memory and register arrays that allows the application of formal equivalence checking for comparing a high-level register tr...
286
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BWCCA
2010
15 years 1 months ago
2010
Network-on-Chip (NoC) architectures provide a good way of realizing efficient interconnections and largely alleviate the limitations of bus-based solutions. NoC has emerged as a so...
159
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ICCAD
2004
IEEE
16 years 3 months ago
2004
IEEE
Microfluidics-based biochips offer a promising platform for massively parallel DNA analysis, automated drug discovery, and real-time biomolecular recognition. Current techniques f...