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» Reuse Technique in Hardware Design
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ICCD
1999
IEEE
122views Hardware» more  ICCD 1999»
15 years 10 months ago
Design and Evaluation of a Selective Compressed Memory System
This research explores any potential for an on-chip cache compression which can reduce not only cache miss ratio but also miss penalty, if main memory is also managed in compresse...
Jang-Soo Lee, Won-Kee Hong, Shin-Dug Kim
FMSD
2002
107views more  FMSD 2002»
15 years 6 months ago
Verification of Out-Of-Order Processor Designs Using Model Checking and a Light-Weight Completion Function
We present a new technique for verification of complex hardware devices that allows both generality andahighdegreeofautomation.Thetechniqueisbasedonournewwayofconstructinga"li...
Sergey Berezin, Edmund M. Clarke, Armin Biere, Yun...
DSD
2011
IEEE
309views Hardware» more  DSD 2011»
14 years 6 months ago
FBMC and GFDM Interference Cancellation Schemes for Flexible Digital Radio PHY Design
—With the opening up of white spaces, efficient use of the fragmented spectrum - TV white space in particular - has become an extremely important focus of research. Apart from ef...
Rohit Datta, Gerhard Fettweis, Zsolt Kollar, P&eac...
ICCAD
2007
IEEE
103views Hardware» more  ICCAD 2007»
16 years 3 months ago
Enhancing design robustness with reliability-aware resynthesis and logic simulation
While circuit density and power efficiency increase with each major advance in IC technology, reliability with respect to soft errors tends to decrease. Current solutions to this...
Smita Krishnaswamy, Stephen Plaza, Igor L. Markov,...
ISQED
2006
IEEE
259views Hardware» more  ISQED 2006»
16 years 12 days ago
Impact of NBTI on SRAM Read Stability and Design for Reliability
— Negative Bias Temperature Instability (NBTI) has the potential to become one of the main show-stoppers of circuit reliability in nanometer scale devices due to its deleterious ...
Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatneka...