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ASPDAC
2007
ACM
119views Hardware» more  ASPDAC 2007»
15 years 10 months ago
Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space
Parallel prefix adder is the most flexible and widely-used binary adder for ASIC designs. Many high-level synthesis techniques have been developed to find optimal prefix structures...
Jianhua Liu, Yi Zhu, Haikun Zhu, Chung-Kuan Cheng,...
ASPDAC
2008
ACM
108views Hardware» more  ASPDAC 2008»
15 years 8 months ago
A new global router for modern designs
- In this paper, we present a new global router, NTHU-Route, for modern designs. NTHU-Route is based on iterative rip-ups and reroutes, and several techniques are proposed to enhan...
Jhih-Rong Gao, Pei-Ci Wu, Ting-Chi Wang
DPHOTO
2009
116views Hardware» more  DPHOTO 2009»
15 years 4 months ago
Interleaved imaging: an imaging system design inspired by rod-cone vision
Under low illumination conditions, such as moonlight, there simply are not enough photons present to create a high quality color image with integration times that avoid camera-sha...
Manu Parmar, Brian A. Wandell
DATE
2004
IEEE
210views Hardware» more  DATE 2004»
15 years 10 months ago
Loop Shifting and Compaction for the High-Level Synthesis of Designs with Complex Control Flow
Emerging embedded system applications in multimedia and image processing are characterized by complex control flow consisting of deeply nested conditionals and loops. We present a...
Sumit Gupta, Nikil Dutt, Rajesh Gupta, Alexandru N...
DATE
2009
IEEE
202views Hardware» more  DATE 2009»
16 years 1 months ago
Design as you see FIT: System-level soft error analysis of sequential circuits
Soft errors in combinational and sequential elements of digital circuits are an increasing concern as a result of technology scaling. Several techniques for gate and latch hardeni...
Daniel Holcomb, Wenchao Li, Sanjit A. Seshia