Sciweavers

2778 search results - page 161 / 556
» Reuse Technique in Hardware Design
Sort
View
DATE
2009
IEEE
163views Hardware» more  DATE 2009»
15 years 10 months ago
Analysis and optimization of fault-tolerant embedded systems with hardened processors
1 In this paper we propose an approach to the design optimization of fault-tolerant hard real-time embedded systems, which combines hardware and software fault tolerance techniques...
Viacheslav Izosimov, Ilia Polian, Paul Pop, Petru ...
WSC
1997
15 years 7 months ago
Automating the Metamodeling Process
Model abstraction using metamodeling has demonstrated the capability to facilitate software reuse, large scale model integration, verification, and validation. Once restricted to...
Don Caughlin
MICRO
2000
IEEE
88views Hardware» more  MICRO 2000»
15 years 6 months ago
Two-level hierarchical register file organization for VLIW processors
High-performance microprocessors are currently designed to exploit the inherent instruction level parallelism (ILP) available in most applications. The techniques used in their de...
Javier Zalamea, Josep Llosa, Eduard Ayguadé...
CSCWD
2009
Springer
16 years 29 days ago
Using Petri Nets to specify collaborative three dimensional interaction
This work presents a methodology to formally model and to build collaborative three dimensional interaction tasks in virtual environments using three different tools: Petri Nets, ...
Rafael Rieder, Marcio Sarroglia Pinho, Alberto Bar...
ISORC
2002
IEEE
15 years 11 months ago
Program Instrumentation for Debugging and Monitoring with AspectC++
Monitoring is a widely-used technique to check assumptions about the real-time behavior of a system, debug the code, or enforce the system to react if certain deadlines are passed...
Daniel Mahrenholz, Olaf Spinczyk, Wolfgang Schr&ou...